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Altera_Forum
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15 years ago

Altera CycloneIII FPGA PLL problem

The PLL input clock is 27M. It is multipied and output a clock of 270M to supply the ASI IP core. 8 PCB boards are in test and downloaded the same FPGA program. The problem is, 4 out of 8 boards can ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Route the input clock to an output pin and check it. If this looks bad, check the solder joints of your clock signal on the board.

Bad joints will introduce reflections and spikes and that makes the PLL to misbehave.

BTW are the faulty PLLs in lock?

-- Ton