altddio_in, altddio_out msb, lsb confusion

Perhaps I can also add that it seems to me that the schemes proposed in the Altera application note on source synchronous interfaces (AN433) wouldn't work very well. (I know it must but I can't see how it does).

i.e. the altddio_in timing requires that the first bit of a pair of bits in a DDR transfer is clocked on the negative edge.

Quote (from the altddio user guide):

"On the falling edge of the clock, the negative-edge triggered register BI acquires the first data bit. On the

corresponding rising edge of the clock, the positive-edge triggered register AI acquires the second data bit."

This would require the transmitted clock to be 270 degrees (or -90) out of phase. AN433 talks about the scheme wherein the clock is 90 degrees out of phase. (And I have based all of my timing on this assumption).

Can anyone put me right on this?

Regards,

D.

I remember being equally confused when I first use these megafunctions. Assuming that nothing has changed since I last used these megafunctions in 6.1:

datain_h is the data that will be driven to pin on rising clock edge

datain_l is the data that will be driven to pin on falling clock edge

dataout_h is the data on the pin while clock was low (captured rising clock edge)

dataout_l is the data on the pin while clock was high (captured falling clock edge)

Connect an altddio_in and an alt_ddio_out together and run a quick sim on it to see the results. The short answer is whatever you clock out on datain_h and datain_l will show up on dataout_l and dataout_h respectively on the following clock cycle.

Jake

Thanks,

I've done a sim and it confirms what you said. It strikes me as a bit strange that it works that way but as long as I understand it then I should be able to make it work.

Regards,

Dave.