altddio_in, altddio_out msb, lsb confusion

Perhaps I can also add that it seems to me that the schemes proposed in the Altera application note on source synchronous interfaces (AN433) wouldn't work very well. (I know it must but I can't see how it does).

i.e. the altddio_in timing requires that the first bit of a pair of bits in a DDR transfer is clocked on the negative edge.

Quote (from the altddio user guide):

"On the falling edge of the clock, the negative-edge triggered register BI acquires the first data bit. On the

corresponding rising edge of the clock, the positive-edge triggered register AI acquires the second data bit."

This would require the transmitted clock to be 270 degrees (or -90) out of phase. AN433 talks about the scheme wherein the clock is 90 degrees out of phase. (And I have based all of my timing on this assumption).

Can anyone put me right on this?

Regards,

D.