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Milan_S's avatar
Milan_S
Icon for New Contributor rankNew Contributor
2 months ago

Agilex 5 input termination differential

Hi, After switching from Quartus 24.3.1 (Build 102) to Quartus 25.1.1 (Build 125), I encountered an issue with signal integrity on my hardware. Differential pairs operating at 400 Mbps (_P/_N) are d...
Core Logic
Generic Io
AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
2 months ago

Hello,

 

We have confirmed that the behavior you are seeing in Quartus Prime Pro 25.1.x is due to a known issue. In these versions, on-chip differential termination (RD_OCT) for True Differential Signaling inputs on HSIO banks is not applied correctly. You can refer to the below link:

Why True Differential input buffer with on-chip differential Termination (RD OCT) enabled does not respond after device is configured for Agilex™ 3 FPGA, Agilex™ 5 FPGA, and Agilex™ 7 FPGA devices? | Altera Community

 

Regards,

Aqid