Forum Discussion
New ContributorAgilex 5 input termination differential
Hi,
After switching from Quartus 24.3.1 (Build 102) to Quartus 25.1.1 (Build 125), I encountered an issue with signal integrity on my hardware. Differential pairs operating at 400 Mbps (_P/_N) are defined as 1.3 V True Differential Signaling with Input Termination – Differential enabled. This configuration works correctly in Quartus 24.3.1. We verified signal integrity using a specialized oscilloscope with a differential probe. As expected, enabling or disabling termination in the Assignment Editor had a significant impact on the signal shape.
However, in Quartus 25.1.1, applying the same configuration does not affect signal integrity. The signal appears as if termination is always disabled, regardless of the ON/OFF setting for Input Termination – Differential.
Is there a change in how differential I/Os with termination should be defined in Quartus 25.1.1? Or is this a potential issue in the new version? All my assignments show OK status, and there are no warnings related to these settings in the design (Ignored Assignments).
3 Replies
Milan_SIt seems that termination works correctly for dedicated clock inputs, but not for HSIOs in Q25.1.1
- AqidAyman_Altera
Regular Contributor
Hello,
We have confirmed that the behavior you are seeing in Quartus Prime Pro 25.1.x is due to a known issue. In these versions, on-chip differential termination (RD_OCT) for True Differential Signaling inputs on HSIO banks is not applied correctly. You can refer to the below link:
Regards,
Aqid
- AqidAyman_Altera
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