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New ContributorAgilex 5 HPS EMIF - Differential Pair Polarity Inversion Support
For the Agilex 5 HPS DDR interface, is P/N swapping (polarity inversion) within a differential pair supported?
I could not find a clear statement in the Agilex 5 EMIF documentation.
Specifically:
- Is polarity inversion supported for HPS DDR differential signals?
- If yes, is any Quartus, HPS EMIF, or firmware configuration required?
- If not, must polarity be preserved at the PCB level?
- Is there a documentation section or application note that explicitly covers this requirement?
I am looking specifically for the Agilex 5 HPS EMIF/DDR interface, not a generic FPGA differential I/O or transceiver interface.
1 Reply
KianHinT_alteraFrequent Contributor
Hi sbj
Apologies for the delay in getting back. I searched through our database and the closest guide for your question is this EMIF IP user guide for Agilex 5 as the memory controller, the PHY, DQS clock trees and byte lane pin mapping are all shared hardware(both fabric and HPS) thus no special separate handling/documentation for just HPS EMIF alone (although there is additional constraints on certain scenarios like restriction and io bank usage)
In the document
it states that both T/C (or P/N) polarity cannot be swapped in the documentation and as HPS shared the same hardware mem controller and IO96 byte lane structure as mentioned above , this requirement is also applicable to HPS EMIF. This also means polarity needs to be preserved at PCB levels
You can also refer to section 3.7 of the same documentation on the HPS EMIF portion for additional requirementsThanks
Regards
Kian
