Yevgenii
New Contributor
New ContributorAgilex 5 CAUI-10, XLAUI, XLPPI Specification supported for 100G Ethernet
Hello.
I'm trying to implement 100G Ethernet
In Agilex™ 5 FPGAs: High-Speed Serial Interface (HSSI) Hard IP
documentation states that Agilex 5 supports these specifications - CAUI-10, XLAUI, XLPPI. But in the GTS PMA/FEC Direct PHY Intel FPGA IP IP core - I can't choose 10 transceiver lines, only 8.
which is not entirely clear, since to support CAUI-10 need to be able to select 10 lines.
Maybe there is another way to implement CAUI-10, another core?
I would like to use an external PHY to implement 100GE, but I don’t see a way to implement this in Agilex™ 5.
I would like to use an external PHY to implement 100GE, but I don’t see a way to implement this in Agilex™ 5.
Assuming I implement the alignment, skew compensation, and bit ordering correctly (use 10 instance GTS IP Core)— would this be a feasible way to receive a CAUI-10 stream?
And if so — does it mean I could also implement CAUI-4 the same way (i.e. aggregating 4×25G manually), given that the transceivers can handle it individually?
