Agilex 5 A5EC065BB32AE5SR0 issue

Question

Hello&nbsp;I built a new board with A5EC065BB32AE5SR0 , I got a issue with the fabric.&nbsp;the FPGA is configurable, and Init done goes to high after configuration .I have a very simple verilog code with PLL output to the pin.&nbsp;But there is no output.&nbsp;could you identify what is the problem here?&nbsp;Atex&nbsp;

sstrell · Answer

Without seeing a design or code, it's pretty much impossible to help.&nbsp; Can you provide more detail and maybe some code?&nbsp; Also what you've tried so far for debugging.

atex-tester · Answer

The code is very simple, a PLL only&nbsp;module test(input CLK_25MHZ_IN,input DDR_REF_CLK0,input DDR_REF_CLK1,input DDR_REF_CLK2,input DDR_REF_CLK3,&nbsp;input AVSTX8W_CLK,&nbsp; //Avalon FIFO clock input&nbsp;//GPIO Interfaceinout [5:0] SYS_GPIO, //Sys GPIO 0 : as command output for cmd doneoutput [2:0] SYS_LED,output &nbsp; &nbsp;DDR_B4_x4_DQ2,output &nbsp; &nbsp;DDR_B4_x4_DQ6,&nbsp;output DDR_1V8_IO0,inout [6:0] GPIO&nbsp;&nbsp;);&nbsp;&nbsp;&nbsp;//assign DDR_B4_x4_DQ6 = AVSTX8W_CLK;//assign DDR_B4_x4_DQ2 = CLK_25MHZ_IN;&nbsp;wire sys_reset;&nbsp;&nbsp;reset u0 (.ninit_done (sys_reset)&nbsp; //&nbsp; output,&nbsp; width = 1, ninit_done.reset);&nbsp;&nbsp;wire sys_pll_locked;wire nios_clk;wire test_clk;SYS_PLL sys_pll (.refclk&nbsp; &nbsp;(AVSTX8W_CLK),&nbsp; &nbsp;//&nbsp; &nbsp;input,&nbsp; width = 1,&nbsp; refclk.clk.locked&nbsp; &nbsp;(sys_pll_locked),&nbsp; &nbsp;//&nbsp; output,&nbsp; width = 1,&nbsp; locked.export.rst&nbsp; &nbsp; &nbsp; (sys_reset),&nbsp; &nbsp; &nbsp; //&nbsp; &nbsp;input,&nbsp; width = 1,&nbsp; &nbsp;reset.reset//.extclk_out (SYS_GPIO[1:0]),.outclk_0 (nios_clk), //&nbsp; output,&nbsp; width = 1, outclk0.clk.outclk_1 (test_clk), //&nbsp; output,&nbsp; width = 1, outclk1.clk.outclk_2 ()&nbsp; //&nbsp; output,&nbsp; width = 1, outclk2.clk);/*reg output_clk;always@(posedge nios_clk) beginoutput_clk &lt;= ~ output_clk;end*/&nbsp;wire sys_rstn;&nbsp;assign sys_rstn = sys_pll_locked &amp; (~sys_reset);&nbsp;assign SYS_LED[0]&nbsp; = sys_rstn? nios_clk : 1'bx;assign SYS_LED[1] = sys_reset;assign SYS_LED[2] = sys_pll_locked;&nbsp;assign GPIO[0] = sys_rstn;assign GPIO[1] = 1'b1;assign GPIO[2] = CLK_25MHZ_IN;assign GPIO[3] = 1'b1;assign GPIO[4] = 1'b0;assign GPIO[5] = 1'b1;assign GPIO[6] = 1'b0;&nbsp;&nbsp;endmodule&nbsp;The voltage is shown on the screenshot above,&nbsp;&nbsp;&nbsp;Temp sensor plot is shown above.&nbsp;Any other files I can provide pls let me know&nbsp;

sstrell · Answer

Are you trying to see this on a flashing LED or are you using a scope?&nbsp; You're not going to be able to see a multi MHz clock flash on an LED.&nbsp; What frequency is nios_clk?&nbsp; Have you made sure that the pin you assigned SYS_LED[0] in the Pin Planner is configured correctly (maybe needs a pull-up?)?

atex-tester · Answer

&nbsp;The led pin is gpio only.nothing is there and test point only. &nbsp;The nios clk is 100mhz, I am using oscilloscope to capture the wave form. A constant one is shown only. Pin assignment is correct. The pll locked is high but nothing came out from the pin&nbsp;

atex-tester · Answer

let me know if more info I need to provide?&nbsp;

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Agilex 5 A5EC065BB32AE5SR0 issue

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