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atex-tester
New Contributor
New ContributorAgilex 5 A5EC065BB32AE5SR0 issue
Hello I built a new board with A5EC065BB32AE5SR0 , I got a issue with the fabric. the FPGA is configurable, and Init done goes to high after configuration . I have a very simple verilog code wit...
atex-testerNew Contributor
New ContributorThe code is very simple, a PLL only
module test
(
input CLK_25MHZ_IN,
input DDR_REF_CLK0,
input DDR_REF_CLK1,
input DDR_REF_CLK2,
input DDR_REF_CLK3,
input AVSTX8W_CLK, //Avalon FIFO clock input
//GPIO Interface
inout [5:0] SYS_GPIO, //Sys GPIO 0 : as command output for cmd done
output [2:0] SYS_LED,
output DDR_B4_x4_DQ2,
output DDR_B4_x4_DQ6,
output DDR_1V8_IO0,
inout [6:0] GPIO
);
//assign DDR_B4_x4_DQ6 = AVSTX8W_CLK;
//assign DDR_B4_x4_DQ2 = CLK_25MHZ_IN;
wire sys_reset;
reset u0 (
.ninit_done (sys_reset) // output, width = 1, ninit_done.reset
);
wire sys_pll_locked;
wire nios_clk;
wire test_clk;
SYS_PLL sys_pll (
.refclk (AVSTX8W_CLK), // input, width = 1, refclk.clk
.locked (sys_pll_locked), // output, width = 1, locked.export
.rst (sys_reset), // input, width = 1, reset.reset
//.extclk_out (SYS_GPIO[1:0]),
.outclk_0 (nios_clk), // output, width = 1, outclk0.clk
.outclk_1 (test_clk), // output, width = 1, outclk1.clk
.outclk_2 () // output, width = 1, outclk2.clk
);
/*
reg output_clk;
always@(posedge nios_clk) begin
output_clk <= ~ output_clk;
end
*/
wire sys_rstn;
assign sys_rstn = sys_pll_locked & (~sys_reset);
assign SYS_LED[0] = sys_rstn? nios_clk : 1'bx;
assign SYS_LED[1] = sys_reset;
assign SYS_LED[2] = sys_pll_locked;
assign GPIO[0] = sys_rstn;
assign GPIO[1] = 1'b1;
assign GPIO[2] = CLK_25MHZ_IN;
assign GPIO[3] = 1'b1;
assign GPIO[4] = 1'b0;
assign GPIO[5] = 1'b1;
assign GPIO[6] = 1'b0;
endmodule
The voltage is shown on the screenshot above,
Temp sensor plot is shown above.
Any other files I can provide pls let me know
