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atex-tester's avatar
atex-tester
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5 days ago

Agilex 5 A5EC065BB32AE5SR0 issue

Hello 

I built a new board with A5EC065BB32AE5SR0 , I got a issue with the fabric. 

the FPGA is configurable, and Init done goes to high after configuration .

I have a very simple verilog code with PLL output to the pin. 

But there is no output. 

could you identify what is the problem here? 

Atex 

Programmable Logic Device

6 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    4 days ago

    Without seeing a design or code, it's pretty much impossible to help.  Can you provide more detail and maybe some code?  Also what you've tried so far for debugging.

  • atex-tester's avatar
    atex-tester
    Icon for New Contributor rankNew Contributor
    4 days ago

    The code is very simple, a PLL only

     

    module test
    (
    input CLK_25MHZ_IN,
    input DDR_REF_CLK0,
    input DDR_REF_CLK1,
    input DDR_REF_CLK2,
    input DDR_REF_CLK3,
     
    input AVSTX8W_CLK,  //Avalon FIFO clock input
     
    //GPIO Interface
    inout [5:0] SYS_GPIO, //Sys GPIO 0 : as command output for cmd done
    output [2:0] SYS_LED,
    output    DDR_B4_x4_DQ2,
    output    DDR_B4_x4_DQ6,
     
    output DDR_1V8_IO0,
    inout [6:0] GPIO
     
     
    );
     
     
     
    //assign DDR_B4_x4_DQ6 = AVSTX8W_CLK;
    //assign DDR_B4_x4_DQ2 = CLK_25MHZ_IN;
     
    wire sys_reset;
     
     
    reset u0 (
    .ninit_done (sys_reset)  //  output,  width = 1, ninit_done.reset
    );
     
     
    wire sys_pll_locked;
    wire nios_clk;
    wire test_clk;
    SYS_PLL sys_pll (
    .refclk   (AVSTX8W_CLK),   //   input,  width = 1,  refclk.clk
    .locked   (sys_pll_locked),   //  output,  width = 1,  locked.export
    .rst      (sys_reset),      //   input,  width = 1,   reset.reset
    //.extclk_out (SYS_GPIO[1:0]),
    .outclk_0 (nios_clk), //  output,  width = 1, outclk0.clk
    .outclk_1 (test_clk), //  output,  width = 1, outclk1.clk
    .outclk_2 ()  //  output,  width = 1, outclk2.clk
    );
    /*
    reg output_clk;
    always@(posedge nios_clk) begin
    output_clk <= ~ output_clk;
    end
    */
     
    wire sys_rstn;
     
    assign sys_rstn = sys_pll_locked & (~sys_reset);
     
    assign SYS_LED[0]  = sys_rstn? nios_clk : 1'bx;
    assign SYS_LED[1] = sys_reset;
    assign SYS_LED[2] = sys_pll_locked;
     
    assign GPIO[0] = sys_rstn;
    assign GPIO[1] = 1'b1;
    assign GPIO[2] = CLK_25MHZ_IN;
    assign GPIO[3] = 1'b1;
    assign GPIO[4] = 1'b0;
    assign GPIO[5] = 1'b1;
    assign GPIO[6] = 1'b0;
     
     
    endmodule
     
    The voltage is shown on the screenshot above, 
     
     

    Temp sensor plot is shown above. 

    Any other files I can provide pls let me know

     
    • atex-tester's avatar
      atex-tester
      Icon for New Contributor rankNew Contributor
      4 days ago

       The led pin is gpio only.nothing is there and test point only.  The nios clk is 100mhz, I am using oscilloscope to capture the wave form. A constant one is shown only. Pin assignment is correct. The pll locked is high but nothing came out from the pin 

      • ShengN_altera's avatar
        ShengN_altera
        Icon for Super Contributor rankSuper Contributor
        2 days ago

        You'll have to use pll clock source with low jitter check this link

        Schematic can be downloaded from installer package link

        For example premium dev kit, I set the location as below:

         

         

        Signal tap result:

        I use issp to toggle the reset:

        issp u0 (
        .source (sys_reset)  //  output,  width = 1, sources.source
        );
  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    4 days ago

    Are you trying to see this on a flashing LED or are you using a scope?  You're not going to be able to see a multi MHz clock flash on an LED.  What frequency is nios_clk?  Have you made sure that the pin you assigned SYS_LED[0] in the Pin Planner is configured correctly (maybe needs a pull-up?)?