After watchdog for dual-config is enabled, the FPGA seems like not work properly every dozens of seconds. Why?

Hi,@JohnT_Intel​

Thanks for your idea.

While there is a problem for us. The serial number will be set by workers in the factory ,then they can only program a file with serial number into FPGA. This will be done independently with the application pof. The worker in factory can't compile FPGA project and they can only do the programming with Jtag. So they just modify the file and download this file directly into UFM. So how will this be realized. Thanks very much!

Hi,

If you would like to add unique serial number into UFM then you can only use hex file to incorporate into POF and program into the UFM.

The other method is to use System ID Periphery Core IP (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_embedded_ip.pdf Chapter 40) to incorporate the ID for each of your system design.

Hi, @JohnT_Intel​

I have another question, could you please help me to solve it? This question is emergency, so I hope it can be resolved as soon as possible. Thanks very much!

The issue is:

Each of our product will have a unique serial number which is 4 bytes long, like 0x"0F0F0F0F". The number will be written into FPGA in our product. But the serial number will be modified for different products when they leave factory. FPGA in the product will read this serial numer when the product operates in customer's place. How can I realize this?

My initial idea is like below:

( I make a file whose content can be edited. The file is edited with 4 bytes's serial number. Then this file can be downloaded into UFM and FPGA could read the serial number from UFM.

But how will I make such a file that can be edited and be programmed into UFM with Jtag or other ways?)

Besides that, are there any other good ways to realize this function except what I proposed? If not, please tell me how to realize the function I proposed.

Thanks very much!

Hi,

This phenomenon is cause by the Max 10 being reconfigured. I would suspect that the reset watchdog timer is not being set. Not sure if you have a way to confirm that your state machine is executing the writing into the reset watchdog timer?

After problem occurs(PHY Link LED become on from off), the SignalTap also go into Invalid Jtag configuration. What can get from this phenomenon?

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Hi,

I will need to further understand your PHY link and how it work on your design to understand what is actually happening to further understand what is happening. The reason is that watchdog timer will cause the Max 10 device to reconfigure if it is not reset correctly.

But only when I enbled the watchdog did problems come, so I think there is sth to do with watchdog. I will go on looking into it and hope you could give me some solutions or comments about this if you have further findings. I would also hope could you please ask about this issue with your colleagues and maybe get some ideas. Thanks very much!

Hi,

You need to look into your PHY Communication interface and check why it is breaking down. I don't think that the watchdog timer can cause any issue on this except that watchdog timer times out and cause reconfiguration to happen.

Yes, there must be sth wrong with enbale watchdog. But I don't know what's the problem so I ask you about this. After all, the problem only happens when I enable watch dog. I still don't know where should I go and Anything else to recommend to look into? So can heip me to find the problem.

Hi,

Thanks for the explanation. It looks like something went wrong when you enable the watchdog timer. I think you will need to signalTap into your design to understand what is causing the PHY communication to break down. Cause the working chip does not face any issue and the reset watchdog timer should be working correctly.