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Altera_Forum's avatar
Altera_Forum
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14 years ago

AD5620 DAC interface

Hi all. I would like to ask for help with my problem.

I am trying to make an DAC interface (serial) using AD5620BRJZ with MAX7000AE (EPM7256AEQC208-C7). Attached is my code in VHDL and a copy of the datasheet for the DAC.

I don't know if this will work. I have not studied how to use ModelSim yet. I only had a crash course about VHDL and Quartus II when this project was turned over to me. And I had to learn on my own.

Please have a look at my code. i would appreciate your comments/suggestions.

Thanks.

Glenn

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hi Glenn,

    I have my doubts that it will work. For example the en input. You use it as write enable for the input data right? But you use it also as enable for DOUT <= shiftout. This confuses me a bit. In addition, you have a free runing counter. You should reset your counter when you begin to writing the data to the dac. What is the clock frequency?

    I recommand you to use ModelSim, this will help you.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Thanks for the reply. Yes, i used the EN input to write data to the shift register. Now that you pointed that out, it confuses me as well. I'll try another way. And, thanks for pointing out the free running counter. I never really thought of that... the frequency of the clock is the same as the global clock which is 20Mhz. i wanted to use PLL to make a slower clock but the device doesn't support it. i wanted to use a counter too but i'm already running out of LABs.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    er, can someone please help me understand how to do this (or rewrite the code, i would really appreciate that.)? i've always had a difficulty with the parallel-in-serial-out shift register. let alone that i need to bring the SYNC signal UP after the 16th negative edge clock. This thing sounds so simple yet i am having a hard time understanding HDL. i am only a beginner.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hy Glenn,

    I think the biggest problem is, that the Sync signal has to go low together with the falling edge of the clock while the data has to be applied on the positive edge of the clock. So what i probably would do in this case is to halfen the dac clock and generate a bitvector for the data that is then shiftet out.

    Try something like that in the attachment. I didn't tested or synthesised it (maybe there are erros inside). It is for sure not the best solution but maybe it helps you to write your own module.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Thank you very much chrigu. i'll take a look at your code..this definitely will help me start at something solid..

    thanks for the help.

    BR

    glenn
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    hello chrigu,

    i was able to use your source code as reference. i only changed o_dac_clk into a clock like output. and i was able to have an output in o_dac_sdin the same with the v_data_buf...

    thank you very much for the help.

    BR

    glenn
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hi glenn

    It was a plesure to help you.

    Best Regards

    Chrigu