AD5620 DAC interface

Hy Glenn,

I think the biggest problem is, that the Sync signal has to go low together with the falling edge of the clock while the data has to be applied on the positive edge of the clock. So what i probably would do in this case is to halfen the dac clock and generate a bitvector for the data that is then shiftet out.

Try something like that in the attachment. I didn't tested or synthesised it (maybe there are erros inside). It is for sure not the best solution but maybe it helps you to write your own module.