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Altera_Forum
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14 years ago

AD5620 DAC interface

Hi all. I would like to ask for help with my problem. I am trying to make an DAC interface (serial) using AD5620BRJZ with MAX7000AE (EPM7256AEQC208-C7). Attached is my code in VHDL and a copy of t...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

er, can someone please help me understand how to do this (or rewrite the code, i would really appreciate that.)? i've always had a difficulty with the parallel-in-serial-out shift register. let alone that i need to bring the SYNC signal UP after the 16th negative edge clock. This thing sounds so simple yet i am having a hard time understanding HDL. i am only a beginner.