Honored ContributorHi,
In my new design i have selected Max10 A7 FPGA. i have a specific constraint for a particular signal. the signal have 480Mbps data rate and it should be connected to LVCMOS 1.2V IO. Is it possible in Max 10 A7 FPGA. I am quiet a beginner in FPGA designs. Regards
Honored ContributorIf you are doing 480 MB USB 2, you should use a USB PHY chip. Look at the schematics of various dev boards with USB to see some examples.
Honored ContributorHi,
We can not use USB PHY chip if we plan to use USB in HSIC mode. In that case,we need to run FPGA IO with 480 mbps data rate. Regards, BhaumikHonored ContributorRefer to page 24 of the MAX 10 max 10 fpga device datasheet (https://www.altera.com/en_us/pdfs/literature/hb/max-10/m10_datasheet.pdf), fOUT max is 472.5MHz for a -6 part.
So, no - you won't support a single ended 480Mbps signal with MAX 10. Cheers, AlexHonored ContributorHello Alex,
But USB HSIC uses DDR method. So clock frequency we require is 240 MHz. Now, can it work? Thanks for your reply. Warm Regards, BhaumikHonored ContributorI wasn't aware USB HSIC uses DDR and none of the previous postings mentioned DDR.
So, as per my other response to sujesh's other post (http://www.alteraforum.com/forum/showthread.php?t=48516), yes it could work. Regards, AlexHonored ContributorHello Alex,
I am grateful to you for your reply. It's one more time you have helped me. Cheers, BhaumikHonored ContributorThanks a lot Friends , thanks for the guidence.
Ya my design is for HSIC which uses DDR for its data signal(and inturn it have to be bidirectional and driven on an LVCMOS 1.2V). Regards Sujesh
