Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Acheiving 480Mbps on Max10 A7 FPGA(FPGA Beginner)

Hi, In my new design i have selected Max10 A7 FPGA. i have a specific constraint for a particular signal. the signal have 480Mbps data rate and it should be connected to LVCMOS 1.2V IO. Is it ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Hello Alex,

But USB HSIC uses DDR method. So clock frequency we require is 240 MHz. Now, can it work?

Thanks for your reply.

Warm Regards,

Bhaumik