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Honored Contributor
Honored ContributorAcheiving 480Mbps on Max10 A7 FPGA(FPGA Beginner)
Hi, In my new design i have selected Max10 A7 FPGA. i have a specific constraint for a particular signal. the signal have 480Mbps data rate and it should be connected to LVCMOS 1.2V IO. Is it ...
Altera_ForumHonored Contributor
Honored ContributorI wasn't aware USB HSIC uses DDR and none of the previous postings mentioned DDR.
So, as per my other response to sujesh's other post (http://www.alteraforum.com/forum/showthread.php?t=48516), yes it could work. Regards, Alex
