We have an Altera Max 10 FPGA chip on one of our circuit boards. We are able to push code to it using bash script but I have no idea how to perform the following functions now that the code is on the fpga: 1. Connect - Connect to the FPGA and confirm that the connection was established 2. Disconnect - Disconnect from the FPGA and confirm that the connection was terminated 3. Read - Read data from the FPGA 4. Write - Write data to the FPGA 5. Run - Run to code on the FPGA 6. Stop - Stop the code running on the FPGA 7. Version - Read back the version of the code on the FPGA In the past we were able to access these functions via the fs2nios.dll, but since the move to the usb blaster I've been unable to find any documentation on the usbblaster.dll to replicate our old methods of accessing the code on the FPGA. Are these commands available in Quartus 18.1? If so can they be automated using tcl scripts? Is there another recommended software for accessing data from the FPGA after the code has been compiled to it?

Connection how? Thru the JTAG interface, or some other means? By 'push code to it' do you mean program your device thru JTAG? Do you implement some type of custom JTAG interface module in your code?Those functions (read data, write data, etc) are not standard embedded JTAG functions. You would have to define JTAG USER0 and/or USER1 functions that are recognized and implement the appropriate features in your logic.

We're connected by means of a usb blaster cable. By push code I mean program the FPGA using bash script to execute files compiled from Quartus Prime. Our test procedures for communicating with the Altera Max10 FPGA were written back before they were bought by intel and the connection was accomplished via the fs2nios cable. Back then there was documentation (I assume) for the fs2nios.dll which was part the cable driver installation software which enabled us to use those functions. After Intel bought Altera they shifted over to the USB Blaster cable and its software contains dll's that serve the same purpose but I haven't been able to find any documentation on how to use its functions. If it was a simple as swapping out one dll for another I'd be golden but it seems I've got to do things the hard way. With Xilinx FPGA's you can alter configurations of the FPGA to get it to perform its necessary functions on the physical level, then write/read to certain I/O elements to perform debugging and diagnostic functions in conjuction with the tasks being performed by the FPGA's physical layer. I'm looking to do something similar with the Altera Max10 FPGA. I found documentation about the external memif toolkit that has a bunch of the functions I'm looking for such as establish_connection (::quartus::external_memif_toolkit) terminate_connection (::quartus::external_memif_toolkit) read_setting (::quartus::external_memif_toolkit) apply_setting (::quartus::external_memif_toolkit) run_connection_command (::quartus::external_memif_toolkit) get_connection_commands (::quartus::external_memif_toolkit) get_connection_info (::quartus::external_memif_toolkit) I have experience using Xilinx and NI FPGA's but unfortunately flavor of them is all very new to me so please forgive me if I confuse you with incorrect terminology. Let me know if I'm on the right track as far as communicating with the FPGA for testing/debugging purposes or if there's a much easier way to accomplish what I'm setting out to do. Thanks!

Well somebody from Intel will have to followup as I have no expertise in the area that you are having issues with. Sorry.

Hi AustinTatious, Allow me some time to look into your issue. I shall come back to you with the findings.

Hello, I guess you are using Linux environment to run the FPGA programming/configuration. If you are using USB Blaster II programming cable to program/config the FPGA over JTAG connector/protocol, it is an easy task. You can use Quartus Programmer tool to program/config the FPGA from your laptop. User guide : https://www.intel.com/content/www/us/en/docs/programmable/683039/21-3/programmer-user-guide.htmlIs this what you looking for? regards,Farabi

Accessing code on a Max10 FPGA | Altera Community

14 Replies

ak6dn
Regular Contributor
3 years ago
Connection how? Thru the JTAG interface, or some other means?

By 'push code to it' do you mean program your device thru JTAG?

Do you implement some type of custom JTAG interface module in your code?
Those functions (read data, write data, etc) are not standard embedded JTAG functions.

You would have to define JTAG USER0 and/or USER1 functions that are recognized and implement the appropriate features in your logic.
- AustinTatious
  New Contributor
  3 years ago
  We're connected by means of a usb blaster cable.
  
  By push code I mean program the FPGA using bash script to execute files compiled from Quartus Prime.
  
  Our test procedures for communicating with the Altera Max10 FPGA were written back before they were bought by intel and the connection was accomplished via the fs2nios cable. Back then there was documentation (I assume) for the fs2nios.dll which was part the cable driver installation software which enabled us to use those functions.
  
  After Intel bought Altera they shifted over to the USB Blaster cable and its software contains dll's that serve the same purpose but I haven't been able to find any documentation on how to use its functions. If it was a simple as swapping out one dll for another I'd be golden but it seems I've got to do things the hard way.
  
  With Xilinx FPGA's you can alter configurations of the FPGA to get it to perform its necessary functions on the physical level, then write/read to certain I/O elements to perform debugging and diagnostic functions in conjuction with the tasks being performed by the FPGA's physical layer. I'm looking to do something similar with the Altera Max10 FPGA.
  
  I found documentation about the external memif toolkit that has a bunch of the functions I'm looking for such as
  
  establish_connection (::quartus::external_memif_toolkit)
  
  terminate_connection (::quartus::external_memif_toolkit)
  
  read_setting (::quartus::external_memif_toolkit)
  
  apply_setting (::quartus::external_memif_toolkit)
  
  run_connection_command (::quartus::external_memif_toolkit)
  
  get_connection_commands (::quartus::external_memif_toolkit) get_connection_info (::quartus::external_memif_toolkit)
  
  I have experience using Xilinx and NI FPGA's but unfortunately flavor of them is all very new to me so please forgive me if I confuse you with incorrect terminology. Let me know if I'm on the right track as far as communicating with the FPGA for testing/debugging purposes or if there's a much easier way to accomplish what I'm setting out to do.
  
  Thanks!
ak6dn
Regular Contributor
3 years ago
Well somebody from Intel will have to followup as I have no expertise in the area that you are having issues with. Sorry.
FakhrulA_altera
Regular Contributor
3 years ago
Hi AustinTatious,

Allow me some time to look into your issue.

I shall come back to you with the findings.
Farabi
Regular Contributor
3 years ago
Hello,

I guess you are using Linux environment to run the FPGA programming/configuration.
If you are using USB Blaster II programming cable to program/config the FPGA over JTAG connector/protocol, it is an easy task.
You can use Quartus Programmer tool to program/config the FPGA from your laptop.
User guide : https://www.intel.com/content/www/us/en/docs/programmable/683039/21-3/programmer-user-guide.html

Is this what you looking for?

regards,
Farabi
AustinTatious
New Contributor
3 years ago
We are using a Windows environment and using the Quartus system-console to run tcl scripts written by our development department. There are .pof and .sof files that we've used to configure the FPGA, but the script relies on the "get_service_paths master" command to populate the global variables used to connect to the fpga, yet the command returns no master service paths. The device service paths show up just fine so we know the jtag connection between the computer and the fpga is functioning, but not the master ones. From my understanding the .pof and .sof files are just used to configure the jtag connection, not to set up services but I could be mistaken. We're not sure how to debug why the master services are appearing when we use the "get_service_paths" proceedure is used. Any assistance would be appreciated.
ak6dn
Regular Contributor
3 years ago
No, the .pof and/or .sof files are used to program the device image, and thus define the complete functionality of the target device.

The basic JTAG interface is defined in hardware (that is how you can access and program a blank device) but the programmed image can add features.

Based on prior comments, I don't see how "get_service_paths master" could return anything other than basic info about an unprogrammed device.

You should be able to (re-)program a (possibly blank) device just using command line tools.

Using "get_service_paths master" before a device is programmed does not seem to be a valid operation to me.
AustinTatious
New Contributor
3 years ago
The library and common tcl files I've been given to work with use the master_write_32, master_read_32 functions pretty extensively. The arguments are "service-path", "address", and "values". The service paths were being populated by the "get_service_paths master" command so at least according to the way the existing code architecture is written it seems pretty important.

Our goal isn't to reprogram or blank the device, but to communicate with it once it has already been programmed using read and write functions. All of our existing code revolves around communicating with the fpga using these master write and read functions. I was trying to not throw the figurative baby out with the bath water because I've been having issues getting their code to work, but if there are other read/write methods I'm not considering that don't rely on the master service path then I'm all ears.
FakhrulA_altera
Regular Contributor
3 years ago
Hi AustinTatious,

I wish to follow up with you about this case.
Do you have any further questions on this matter?
Else I would like to have your permission to close this forum ticket.

Regards,
Fakhrul
AustinTatious
New Contributor
3 years ago
No I don't want to close this ticket yet. My master service still isn't functioning and its the core of my code's functionality. I have the .pof and .sof files but I'm not sure how to debug why this master service isn't functioning. Is it possible to debug it with just these files or do I need the project file? Does the master service need to be instantiated correctly before those files are compiled or is there a way to initialize it from the tcl console?
FvM
Super Contributor
3 years ago
I'm under the impression that your problems are mainly related to missing function of the FS2 third party tools. This might be a problem of newer Windows or incompatibility with recent Quartus versions. First Silicon Solutions seems to have stopped this business since many years, in so far I'm not sure what Intel support can do about it.