Forum Discussion
New ContributorAccessing code on a Max10 FPGA
We have an Altera Max 10 FPGA chip on one of our circuit boards. We are able to push code to it using bash script but I have no idea how to perform the following functions now that the code is on the fpga:
1. Connect - Connect to the FPGA and confirm that the connection was established
2. Disconnect - Disconnect from the FPGA and confirm that the connection was terminated
3. Read - Read data from the FPGA
4. Write - Write data to the FPGA
5. Run - Run to code on the FPGA
6. Stop - Stop the code running on the FPGA
7. Version - Read back the version of the code on the FPGA
In the past we were able to access these functions via the fs2nios.dll, but since the move to the usb blaster I've been unable to find any documentation on the usbblaster.dll to replicate our old methods of accessing the code on the FPGA.
Are these commands available in Quartus 18.1? If so can they be automated using tcl scripts? Is there another recommended software for accessing data from the FPGA after the code has been compiled to it?
14 Replies
FakhrulA_alteraRegular Contributor
Hi AustinTatious,
Allow me some time to look into your issue.
I shall come back to you with the findings.
ak6dnWell somebody from Intel will have to followup as I have no expertise in the area that you are having issues with. Sorry.
- ak6dn
Connection how? Thru the JTAG interface, or some other means?
By 'push code to it' do you mean program your device thru JTAG?
Do you implement some type of custom JTAG interface module in your code?
Those functions (read data, write data, etc) are not standard embedded JTAG functions.You would have to define JTAG USER0 and/or USER1 functions that are recognized and implement the appropriate features in your logic.
AustinTatiousWe're connected by means of a usb blaster cable.
By push code I mean program the FPGA using bash script to execute files compiled from Quartus Prime.
Our test procedures for communicating with the Altera Max10 FPGA were written back before they were bought by intel and the connection was accomplished via the fs2nios cable. Back then there was documentation (I assume) for the fs2nios.dll which was part the cable driver installation software which enabled us to use those functions.
After Intel bought Altera they shifted over to the USB Blaster cable and its software contains dll's that serve the same purpose but I haven't been able to find any documentation on how to use its functions. If it was a simple as swapping out one dll for another I'd be golden but it seems I've got to do things the hard way.
With Xilinx FPGA's you can alter configurations of the FPGA to get it to perform its necessary functions on the physical level, then write/read to certain I/O elements to perform debugging and diagnostic functions in conjuction with the tasks being performed by the FPGA's physical layer. I'm looking to do something similar with the Altera Max10 FPGA.
I found documentation about the external memif toolkit that has a bunch of the functions I'm looking for such as
establish_connection (::quartus::external_memif_toolkit)terminate_connection (::quartus::external_memif_toolkit)read_setting (::quartus::external_memif_toolkit)apply_setting (::quartus::external_memif_toolkit)run_connection_command (::quartus::external_memif_toolkit)get_connection_commands (::quartus::external_memif_toolkit) get_connection_info (::quartus::external_memif_toolkit)I have experience using Xilinx and NI FPGA's but unfortunately flavor of them is all very new to me so please forgive me if I confuse you with incorrect terminology. Let me know if I'm on the right track as far as communicating with the FPGA for testing/debugging purposes or if there's a much easier way to accomplish what I'm setting out to do.
Thanks!
