a simple code showing a latch in quartus II?

Hi i am working in system verilog and a simple code like

always_ff @ (posedge clk , negedge rst_n)

begin

if (rst_n==1'b1)

begin

x<=a;

elseif (i==1'b1)

begin

x<=x+1'b1;

end

end

i am not using the exact name but the code is exactly the same where i is an input pin to the module.

its showing 2 warnings

Warning (13004): Presettable and clearable registers converted to equivalent circuits with latches. Registers power-up to an undefined state, and DEVCLRn places the registers in an undefined state.

and

Warning (335093): Timing Analysis is analyzing one or more combinational loops as latches

for x these warning are coming.

Thanks