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Altera_Forum
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14 years ago

a simple code showing a latch in quartus II?

Hi i am working in system verilog and a simple code like always_ff @ (posedge clk , negedge rst_n) begin if (rst_n==1'b1) begin x<=a; elseif (i==1'b1) begin ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Yes i was facing an additional delay when i checked the timing reports.

Thanks for the reason...