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Altera_Forum
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14 years ago

a simple code showing a latch in quartus II?

Hi i am working in system verilog and a simple code like always_ff @ (posedge clk , negedge rst_n) begin if (rst_n==1'b1) begin x<=a; elseif (i==1'b1) begin ...
Altera_Forum's avatar
Altera_Forum
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14 years ago

You can expect this warning for all recent FPGA families that don't have both asynchronous set and reset provided with their registers. They need to implement a rather complex circuit with a XORed data path on both sides of the register and a latch holding the asynchronous preset value. Besides the reported restrictions, the construct involves additional delay.

The preferred solution is to avoid an asynchronous variable preset.