Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributora simple code showing a latch in quartus II?
Hi i am working in system verilog and a simple code like always_ff @ (posedge clk , negedge rst_n) begin if (rst_n==1'b1) begin x<=a; elseif (i==1'b1) begin ...
Altera_ForumHonored Contributor
Honored ContributorYou can expect this warning for all recent FPGA families that don't have both asynchronous set and reset provided with their registers. They need to implement a rather complex circuit with a XORed data path on both sides of the register and a latch holding the asynchronous preset value. Besides the reported restrictions, the construct involves additional delay.
The preferred solution is to avoid an asynchronous variable preset.
