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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

A little help with verilog please.

wire ts_irig_wire; 
reg  ts_irig;
           
        always @(posedge clk_c0)
        begin
            ts_irig <= {bit_num_cont6,bit_num_cont5,bit_num_cont4,bit_num_cont3,bit_num_cont2,bit_num_cont1};
        end
    
assign ts_irig_wire = ts_irig;

Hello to everyone! This code is giving me this error: 

Error (10133): Verilog HDL Expression error at fpga.v(226): illegal part select of unpacked array "ts_irig_wire"

I can't figure out why, anyone could give me a hand please?

THanks

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    instead of

    wire ts_irig_wire[23:0];

    you should write

    wire [23:0] ts_irig_wire;

    like you have done with the register declaration.

    there is a difference where you place the brackets [] as FvM explained.

    wire [N:0] wirename [0:M];

    defines an array with a width of [N:0] and [0:M] elements

    in your case it has a width of 1 and [23:0] elements

    so you have defined an array.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Thanks, so a declaration of

    wire [23:0] wirename is a 24 bits bus

    and a declaration of

    wire wirename[23:0] consists in 24 wires of 1 bit?