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Altera_Forum
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15 years ago

A little help with verilog please.

wire ts_irig_wire; reg ts_irig; always @(posedge clk_c0) begin ts_irig <= {bit_num_cont6,bit_num_cont5,bit_num_cont4,bit_num_cont3,bit_num_cont2,bit_num_co...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

wire ts_irig_wire[23:0] is an array, not a vector definition.