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Honored Contributor
Honored ContributorA little help with verilog please.
wire ts_irig_wire;
reg ts_irig;
always @(posedge clk_c0)
begin
ts_irig <= {bit_num_cont6,bit_num_cont5,bit_num_cont4,bit_num_cont3,bit_num_cont2,bit_num_co...
Altera_ForumHonored Contributor
Honored Contributorinstead of
wire ts_irig_wire[23:0]; you should write wire [23:0] ts_irig_wire; like you have done with the register declaration. there is a difference where you place the brackets [] as FvM explained. wire [N:0] wirename [0:M]; defines an array with a width of [N:0] and [0:M] elements in your case it has a width of 1 and [23:0] elements so you have defined an array.
