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Altera_Forum
Honored Contributor
Honored ContributorA little help with verilog please.
wire ts_irig_wire;
reg ts_irig;
always @(posedge clk_c0)
begin
ts_irig <= {bit_num_cont6,bit_num_cont5,bit_num_cont4,bit_num_cont3,bit_num_cont2,bit_num_co...
Altera_ForumHonored Contributor
Honored ContributorThanks for the support, it's working :D
