7segment decoder

The variable declaration needs to be put in the function body, not in the package declaration. Also you cannot assign a value to an input port (in your case 'a'). Furthermore you need to use '<=' to assign a value to a signal or an output port.

package sevenDecoderLib is
  type sevenSegment is array(7 downto 1) of bit;
  
  function integer2SevenSegment(i: in integer range 0 to 15) return sevenSegment;
  end package sevenDecoderLib;
package body sevenDecoderLib is
  function integer2SevenSegment(i: in integer range 0 to 15) return 
    sevenSegment is 
       variable segment: sevenSegment;
    begin
      case i is
       when  0=> segment := "1111100"; 
       when  1=> segment := "0110000";
       when  2=> segment := "1101001";
       when  3=> segment := "1111001";
       when  4=> segment := "0110011";
       when  5=> segment := "1011011";
       when  6=> segment := "1011111";
       when  7=> segment := "1110000";
       when  8=> segment := "1111111";
       when  9=> segment := "1111011";
       when 10=>segment := "1110111";
       when 11=>segment := "0011111";
       when 12=>segment := "1001110";
       when 13=>segment := "0111101";
       when 14=>segment := "1001111";
       when 15=>segment := "1000111";
      end case;
   return segment;
  end integer2SevenSegment;
end sevenDecoderLib;
Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
Library work;
use work.sevenDecoderLib.all;
entity Lab5 is 
  port (
    a       : in integer range 0 to 15; 
    output  : out std_logic_vector(7 downto 0)
    );
  end entity;
architecture behave of Lab5 is
  begin
    -- a := 1 ;
    output <= integer2SevenSegment(a);
  end behave;

Thank You for replying,

you cannot initialise A in here because it is an input, you need to initilaise it at it's source. Also, all input/outputs are already signals.

Okay it made sense,

redefine sevenSegment as a std_logic vector. The bit type is hardly ever used:

subtype sevenSegment is std_logic_vector(7 downto 1);