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Altera_Forum's avatar
Altera_Forum
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15 years ago

7segment decoder

This is my code for a 7segment decoder, but I get an error! package sevenDecoderLib is type sevenSegment is array(7 downto 1) of bit; variable segment: sevenSegment; function ...
Altera_Forum's avatar
Altera_Forum
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15 years ago

redefine sevenSegment as a std_logic vector. The bit type is hardly ever used: 

subtype sevenSegment is std_logic_vector(7 downto 1);

VHDL is a strongly typed language, and won't automatically convert types for you. The string is by default a std_logic_vector IIRC, and as your variable is an array of bits you would need to convert the vector first. It is easier to declare your variable as a std_logic_vector instead.