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Altera_Forum's avatar
Altera_Forum
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13 years ago

2.5V VCIO for Configuration Pins

I am using a Cyclone III. I want to use the LVDS IO on Bank 1. I assume that I must set the VIO for Bank 1 to 2.5V.

So now I assume I must use the 2.5V IO standard for the configuration pins that will connect to a EPCS16 serial configuration EEPROM. So VCC for the EPCS16 will also be 2.5V.

The USB Blaster I wish to connect to the EPCS16, to program it, says to connect 3.3V for the VCC(TRGT) pin.

Should I use 2.5V on the USB Blaster header or is there another approach?:confused:

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Alright, I have found some answers. It is more difficult to use the LVDS in Bank 1 and use the EPCS16 to configure the FPGA.

    The documentation on configuring the Cyclone III has the following note:

    The Quartus II software prohibits you from using the LVDS I/O standard in I/O

    Bank 1 when the configuration device I/O voltage is not 2.5 V. If you need to assign

    LVDS I/O standard in I/O Bank 1, navigate to

    Assignments>Device>Settings>Device and Pin Option>Configuration to change the

    Configuration Device I/O voltage to 2.5 V or Auto.

    That takes care of the IO assignment in Quartus. In order to translate the EPCS16's

    3.3V IO to 2.5V IO of Bank 1, I will use a SN74AUP1G08 (SOT package) for each signal

    into the FPGA (ie DATA(0) and nCONFIG). For AS configuration signals driven from the

    FPGA to the EPCS16 (DCLK, ASDI, nCS) the 2.00V Voh min spec of the FPGA meets the

    EPCS16's 1.98V Vih max spec.

    Am I missing something?
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    I will use a SN74AUP1G08 (SOT package) for each signal

    into the FPGA (ie DATA(0) and nCONFIG).

    Am I missing something?

    --- Quote End ---

    Is the 4.3ns delay of the SN74AUP1G08 going to be an issue?

    I vaguely recall someone else using level translators on the forum, and their buffer did cause a problem ...

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Altera is suggesting in several places not to use buffers for the serial flash interface. Of course it may work though, particularlywith fast logic series like AUP.

    My personal fovourite would be to operate the EPCS device at a reduced 3.3V voltage, e.g. 2.8-3 V that will give sufficient voltage margin for the EPCS input signals. Or try with 2.5V compatible M25PX16. It's downwards compatible to M25P16/EPCS16, except for the unsupported electronic signature with command 0xAB. Signature check can be disabled in Quartus, but I didn't yet try.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Thank you very much for the suggestions and cautions. The 74AUP voltage translation could delay the data back to the FPGA (AS config mode) as much as 4.5ns. The data out of the EPCS following the falling edge of the DCLK from the FPGA could lag up to 8ns. With a 40 MHz (maximum) DCLK data from the EPCS would not setup at the FPGA before the next rising edge of DCLK.

    But wait. I do not have timing diagrams for what the Cyclone III is doing with the serial transfer. Does it latch the serial data on the rising or falling edge of DCLK?

    I do have timing diagrams for the EPCS16. This is a bit confusing here also. The device specifies a "Fast Read Clock frequency" at 40MHz max. However, it also specifies a DCLK High Time and a DCLK Low Time of 25ns min. This implies a clock frequency no faster than 20 MHz.

    If I had 25 ns between clock edges I would not have an issue with the propagation delay of the voltage translation.

    Any insight here?
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Did I forget to ask that question first? I do have another board with the Cyclone III and an EPCS16. Perhaps I should put a scope on it and measure the DCLK for this board. I would prefer some datasheet timing diagrams so my empirical measurement does not fool me.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Have you considered using a bus switch, rather than a buffer?

    For example, consider using this part:

    http://www.ti.com/lit/ds/symlink/sn74cb3t1g125.pdf

    Your FPGA VCCIO bank powered at 2.5V would output csN and DCLK to the FPGA with 2.5V logic levels. With the EPCS powered at 3.3V, Vih(min) = 0.6*Vcc = 2V, so the FPGA signals do not need level translation. The EPCS will output a voltage of at least Voh(min) = Vcc - 0.2 = 3.1V.

    If you look at the sn74cb3t1g125 data sheet page 6, you can see the input-to-output response for two different power supply voltages. It looks like you could power the bus switch at 2.5V, and that would clamp the EPCS DATA signal to a little over 2V. The bus switch delay is less than 250ps.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Yes, I think we have a winner !! So many chips. so little time. Thanks