2.5V VCIO for Configuration Pins

Alright, I have found some answers. It is more difficult to use the LVDS in Bank 1 and use the EPCS16 to configure the FPGA.

The documentation on configuring the Cyclone III has the following note:

The Quartus II software prohibits you from using the LVDS I/O standard in I/O

Bank 1 when the configuration device I/O voltage is not 2.5 V. If you need to assign

LVDS I/O standard in I/O Bank 1, navigate to

Assignments>Device>Settings>Device and Pin Option>Configuration to change the

Configuration Device I/O voltage to 2.5 V or Auto.

That takes care of the IO assignment in Quartus. In order to translate the EPCS16's

3.3V IO to 2.5V IO of Bank 1, I will use a SN74AUP1G08 (SOT package) for each signal

into the FPGA (ie DATA(0) and nCONFIG). For AS configuration signals driven from the

FPGA to the EPCS16 (DCLK, ASDI, nCS) the 2.00V Voh min spec of the FPGA meets the

EPCS16's 1.98V Vih max spec.

Am I missing something?