2.5V VCIO for Configuration Pins

Thank you very much for the suggestions and cautions. The 74AUP voltage translation could delay the data back to the FPGA (AS config mode) as much as 4.5ns. The data out of the EPCS following the falling edge of the DCLK from the FPGA could lag up to 8ns. With a 40 MHz (maximum) DCLK data from the EPCS would not setup at the FPGA before the next rising edge of DCLK.

But wait. I do not have timing diagrams for what the Cyclone III is doing with the serial transfer. Does it latch the serial data on the rising or falling edge of DCLK?

I do have timing diagrams for the EPCS16. This is a bit confusing here also. The device specifies a "Fast Read Clock frequency" at 40MHz max. However, it also specifies a DCLK High Time and a DCLK Low Time of 25ns min. This implies a clock frequency no faster than 20 MHz.

If I had 25 ns between clock edges I would not have an issue with the propagation delay of the voltage translation.

Any insight here?