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Altera_Forum's avatar
Altera_Forum
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13 years ago

2.5V VCIO for Configuration Pins

I am using a Cyclone III. I want to use the LVDS IO on Bank 1. I assume that I must set the VIO for Bank 1 to 2.5V. So now I assume I must use the 2.5V IO standard for the configuration pins ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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I will use a SN74AUP1G08 (SOT package) for each signal

into the FPGA (ie DATA(0) and nCONFIG).

Am I missing something?

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Is the 4.3ns delay of the SN74AUP1G08 going to be an issue?

I vaguely recall someone else using level translators on the forum, and their buffer did cause a problem ...

Cheers,

Dave