2.5V VCIO for Configuration Pins

Have you considered using a bus switch, rather than a buffer?

For example, consider using this part:

http://www.ti.com/lit/ds/symlink/sn74cb3t1g125.pdf

Your FPGA VCCIO bank powered at 2.5V would output csN and DCLK to the FPGA with 2.5V logic levels. With the EPCS powered at 3.3V, Vih(min) = 0.6*Vcc = 2V, so the FPGA signals do not need level translation. The EPCS will output a voltage of at least Voh(min) = Vcc - 0.2 = 3.1V.

If you look at the sn74cb3t1g125 data sheet page 6, you can see the input-to-output response for two different power supply voltages. It looks like you could power the bus switch at 2.5V, and that would clamp the EPCS DATA signal to a little over 2V. The bus switch delay is less than 250ps.

Cheers,

Dave