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Altera_Forum's avatar
Altera_Forum
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12 years ago

15fps to 60fps video conversion

I believe somebody had similar problem, but I simply cannot find it.

I want to display my 15fps 1920x1080 video @33MHz on HDTV monitor accepting 60fps framerate, running at approximately @133MHz. So I need to introduce some kind of frame copying.

For that I need to use external SDRAM (my board is DE2-115).

The obvious solution (to me) was to use components from Video and Image Processing Suite, especially since my system will also include NIOS II.

So I use Clocked Video Input to accept 15fps video stream, connect it to a Frame Buffer with Frame Repetition enabled, and finally connect the Frame Buffer to Clocked Video Output to output 60fps video. Please take a look at the drawing in the attachment. In the beginning, I used 100MHz clock for all the video blocks in the SOPC builder system, concerned about SDRAM controller maximum clock rate. I connected underflow output from the Clocked Video Output to a LED on the board to see if underflow occurs.

And it does. My monitor is “on”, meaning it does not enter stand by, but there is no video, only black pixels all over the surface. And the underflow LED turns on, as I said.

I confirmed Clocked Video Output settings (dvi preset) alone, connecting Test Pattern Generator from the VIP suite to the Clocked Video Output, and it works well, so the problem is not there.

I also tried different clock rates for video components and SDRAM, overclocking SDRAM up to 133MHz. No change...

Tried SignalTap II Logc Analyzer, I see good output data to the monitor, and the data values are as I expect. But the display remains black, and there is underflow.

Does anybody have an idea what I might be doing wrong here?

Many thanks in advance.

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    You should address the underflow before chasing the 'black screen' since they may or may not be the same problem.

    Basically, your system (from SDRAM component all the way through to the DVI connector) need to have enough bandwidth and buffering to accommodate your desired pixel rate and latency/overhead (SDRAM refreshes, Avalon-ST packet overhead, etc.)

    Clocked Video Output is pretty simple, and your underflow basically boils down to the FIFO running out of data. Should you care to, you can watch it happen with SignalTap by watching the Frame Buffer/Clocked Video FIFO's and the Avalon-MM Slave in the SDRAM. But for starters, your diagram shows data being pushed onto the FIFO at 100MHz, and popped from the FIFO at 133MHz.

    In general, I would recommend the following:

    - run your entire system at 133MHz (Avalon-ST, SDRAM, Clocked Video Output).

    - make sure the Frame Buffer Avalon-MM master port width matches the SDRAM port width.

    - increase the Frame Buffer burst target and FIFO depth

    - increase the Clocked Video Output embedded FIFO depth

    I'm not familiar with the DE2-115, but you used the word "overclocking" when describing the SDRAM @ 133MHz - what component is on the board and what it is it's maximum frequency?
  • Altera_Forum's avatar
    Altera_Forum
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    Thank you for the reply.

    In the user guide for the board, it states that the on-board SDRAM maximum frequency is approximately 125MHz.

    It is a Cyclone IVE board, with two IS42S16320B-7TL SDRAM modules connected in parallel so the effective data width is 32 bits.

    Datasheet for the component states the maximum frequency is 143MHz.

    Referring to your advices:

    - now the entire system runs on 133MHz, with SDRAM clock being phase shifted for -65 degrees.

    - Frame Buffer Avalon-MM master port matches the SDRAM port width, being 32.

    - I increased both the Frame Buffer burst target and FIFO depth to maximum values available in the GUI

    - I increased the Clocked Video Output embedded FIFO depth to be twice a line length (app 4k)

    I see no progress with these.
  • Altera_Forum's avatar
    Altera_Forum
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    --- Quote Start ---

    In the user guide for the board, it states that the on-board SDRAM maximum frequency is approximately 125MHz.

    --- Quote End ---

    Please check that point again. I believe you are reading the SRAM description.

    --- Quote Start ---

    It is a Cyclone IVE board, with two IS42S16320B-7TL SDRAM modules connected in parallel so the effective data width is 32 bits.

    Datasheet for the component states the maximum frequency is 143MHz.

    --- Quote End ---

    Well, at least you've got 10MHz more available should you choose to pursue it.

    --- Quote Start ---

    I see no progress with these.

    --- Quote End ---

    You're going to have to investigate further; theres a chance you still have an inefficient configuration of the SDRAM / Avalon-MM which might clear things up for you. And if push came to shove, I believe you can also get away with disabling SDRAM refreshes. But before pursuing that with any substantial effort, I would first confirm the problem using SignalTap to watch it happen and possibly decreasing the Clocked Video Output rate until you identify a working configuration, so you can get an idea of exactly how far away you are from your goal.
  • Altera_Forum's avatar
    Altera_Forum
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    You are right, I messed up SRAM and SDRAM. OK, I could go up to 143MHz for sure.

    I experimented a bit, just to make sure that what I want to achieve is actually possible (converting 15fps HDTV to 60fps HDTV).

    So I directly connected VIPSuite's test pattern generator to the Clocked Video Output again. Avalon-ST frequency is 150MHz now (please take a look at the first attached drawing). The generator outputs uniform red background with one pixel thick black frame. And I have it on the display. Great.

    Now, in order to prove my concept, I inserted a Frame Buffer between Test Pattern Generator and Clocked Video Output. Avalon-ST and all the other frequencies are 150MHz (SDRAM is overclocked slightly now); please take a look at the second attached drawing. Should be OK, I presume. But, no video on the display only a floating box on the black background letting me know that the frequency is out of range, that is the vertical refresh rate is 34.3Hz?? How comes? The underflow LED is on in the same time. I caught the moment underflow goes high after power up in signal tap (the third drawing). What I see is that there is underflow occurring as soon as the middle of the third output line, and the fourth line is already corrupt.

    I guess I cannot lower Clocked Video Output rate much, as the display will not work for frame rates much less than 60fps. Will experiment a bit though
  • Altera_Forum's avatar
    Altera_Forum
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    Don't forget the writer side of the Frame Buffer also requires SDRAM bandwidth. With the Test Pattern Generator at 150MHz, I think you are distorting your results because the writer side will attempt to consume all of the available bandwidth. Add a second slower clock for the Test Pattern Generator to run from (15MHz? 1MHz? doesn't matter, you just need one frame to make it to the buffer).

    In the 150MHz domain in your SignalTap, throw in the Avalon-ST 'valid' and 'ready' signals, and the Avalon-MM 'waitrequest' and 'readdatavalid' signals. This will give you an idea of how efficiently you're moving data to/from SDRAM (you want to see long contiguous bursts of 'valid')
  • Altera_Forum's avatar
    Altera_Forum
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    Thank you for your effort Ted! It is highly appreciated.

    Unfortunately, I cannot lower the Test Pattern Generator frequency, since Frame Buffer requests the same clock on writer and reader sides. There is no parameter for the TPG's framerate, it fires all the time at the Avalon-ST clock rate.
  • Altera_Forum's avatar
    Altera_Forum
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    I think you can run the TPG at the slower clock and put a Avalon-ST DCFIFO (with packet support) between the TPG and VFB to act as a clock crossing bridge. Use the Qsys "Insert Avalon-ST Adapters" to automatically insert the necessary adapters after adding the FIFO.