10M25DAF484C8G clock input

Hi,

If voltage of CML and LVDS are not the same, can use below:

If low speed, you can use voltage divider.

If high speed, you need to use level shifter.

If voltage of CML and LVDS are same, not need to use.

And also the external termination circuit:

https://www.intel.com/content/www/us/en/docs/programmable/683760/22-1/lvds-1-8-v-lvds-mini-lvds-and-rsds-receiver.html

The Max 10 lvds IO Standard can refer this :

https://www.intel.com/content/www/us/en/docs/programmable/683760/24-1/lvds-serdes-i-o-standards-support.html

Thanks,

Regards,

Sheng

Hi,

This is example of level shifter:

https://www.analog.com/en/products/max9376.html

Guarantee for high speed.

Thanks,

Regards,

Sheng

Hi,

you usually don't need a level shifter for clock signal. For clock belo 500 MHz, MAX 10 LVDS input has 0.05 - 1.8 V common mode range which most likely fits the CML signal. If not, you can use AC coupling with bias to 1.25 V on the FPGA side.

Similarly, LVDS output driver will most likely fit level requirements of CML input on other device.

Regards
Frank

Hi,

AC coupling circuit can refer here:

https://www.intel.com/content/www/us/en/docs/programmable/683760/22-1/lvpecl-external-termination.html

Thanks,

Regards,

Sheng

Hi Joe,

Reply to this post community.intel.com/t5/Programmable-Devices/10M25DAF484C8G-clock-input/m-p/1718285#M101342:

No. Check this https://www.intel.com/content/www/us/en/docs/programmable/683760/22-1/lvds-channels-support.html

However, only the bottom I/O banks support true LVDS output buffers.

Intel® MAX® 10 I/O Banks Locations:

https://www.intel.com/content/www/us/en/docs/programmable/683105/current/i-o-banks-locations.html

Thanks,

Regards,

Sheng