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joe_su's avatar
joe_su
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5 months ago

10M25DAF484C8G clock input

Hi we have serveral CML clocks output from ethernet PHY which is connected to 10M25DAF484C8G pin P3/R3, V9/V10, how to design the convertion circuit as CML(PHY) to LVDS(max10) ? and if we want to ...
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
5 months ago

Hi,


If voltage of CML and LVDS are not the same, can use below:

If low speed, you can use voltage divider.

If high speed, you need to use level shifter.


If voltage of CML and LVDS are same, not need to use.


And also the external termination circuit:

https://www.intel.com/content/www/us/en/docs/programmable/683760/22-1/lvds-1-8-v-lvds-mini-lvds-and-rsds-receiver.html


The Max 10 lvds IO Standard can refer this :

https://www.intel.com/content/www/us/en/docs/programmable/683760/24-1/lvds-serdes-i-o-standards-support.html


Thanks,

Regards,

Sheng


joe_su's avatar
joe_su
Icon for New Contributor rankNew Contributor
5 months ago

Hi ShengN

one morequestion

I used 10M25DAF484C8G, I need pin L8/L9 configure as diff LVDS output. but IO_1B is on 3.3V power rail.

is it can work on output diff-LVDS clock signal ?

//Joe