Forum Discussion
joe_su
New Contributor
New Contributor10M25DAF484C8G clock input
Hi we have serveral CML clocks output from ethernet PHY which is connected to 10M25DAF484C8G pin P3/R3, V9/V10, how to design the convertion circuit as CML(PHY) to LVDS(max10) ? and if we want to ...
FvM
Super Contributor
Super ContributorHi,
you usually don't need a level shifter for clock signal. For clock belo 500 MHz, MAX 10 LVDS input has 0.05 - 1.8 V common mode range which most likely fits the CML signal. If not, you can use AC coupling with bias to 1.25 V on the FPGA side.
Similarly, LVDS output driver will most likely fit level requirements of CML input on other device.
Regards
Frank
