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joe_su's avatar
joe_su
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11 months ago

10M25DAF484C8G clock input

Hi we have serveral CML clocks output from ethernet PHY which is connected to 10M25DAF484C8G pin P3/R3, V9/V10, how to design the convertion circuit as CML(PHY) to LVDS(max10) ? and if we want to ...
ShengN_altera's avatar
ShengN_altera
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11 months ago

Hi Joe,


Reply to this post community.intel.com/t5/Programmable-Devices/10M25DAF484C8G-clock-input/m-p/1718285#M101342:

No. Check this https://www.intel.com/content/www/us/en/docs/programmable/683760/22-1/lvds-channels-support.html

However, only the bottom I/O banks support true LVDS output buffers.


Intel® MAX® 10 I/O Banks Locations:

https://www.intel.com/content/www/us/en/docs/programmable/683105/current/i-o-banks-locations.html


Thanks,

Regards,

Sheng