We are using CycloneIII EP3C55 FPGA, With configuration flash of EPCS16. We want to perform timing analysis for writing of data from FPGA to Flash. I want the DCLK to Serial data out delay for the FPGA.

Hi Rajaram,

May i know what is the reason to delay the DCLK? Are you connecting the flash memory device with 2 FPGA? Please clarify.

Regards,

YL

Hi YL,

I am not delaying the DCLK,

I want the time delay between DCLK and Valid data given out by FPGA.

Thanks,

Raja

Hi Raja,

Thanks for the clarification. If you are looking for the delay for configuration pin. You may refer to datasheet at link below:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyc3/cyc3_ciii52001.pdf (Page 17)

Regards,

YL