Forum Discussion
RMath11
New Contributor
6 years agoHi YL,
I am not delaying the DCLK,
I want the time delay between DCLK and Valid data given out by FPGA.
Thanks,
Raja
Hi YL,
I am not delaying the DCLK,
I want the time delay between DCLK and Valid data given out by FPGA.
Thanks,
Raja