Forum Discussion
RMath11
New Contributor
7 years agoWe are using CycloneIII EP3C55 FPGA, With configuration flash of EPCS16. We want to perform timing analysis for writing of data from FPGA to Flash. I want the DCLK to Serial data out delay for the FPGA.
RMath11
New Contributor
7 years agoHi YL,
I am not delaying the DCLK,
I want the time delay between DCLK and Valid data given out by FPGA.
Thanks,
Raja