Forum Discussion
RMath11
New Contributor
7 years agoWe are using CycloneIII EP3C55 FPGA, With configuration flash of EPCS16. We want to perform timing analysis for writing of data from FPGA to Flash. I want the DCLK to Serial data out delay for the FPGA.
YuanLi_S_Intel
Regular Contributor
7 years agoHi Rajaram,
May i know what is the reason to delay the DCLK? Are you connecting the flash memory device with 2 FPGA? Please clarify.
Regards,
YL