Verilog delays~?

So I built this... but....

always @(posedge read_flash_pixel or posedge flash_pause_done) begin

if (read_flash_pixel) begin

flash_pause <= 1;

end else begin

flash_pause <= 0;

end

end

always @(posedge CLOCK_50) begin

if(flash_pause == 1) begin

flash_pause_count <= flash_pause_count+1;

if (flash_pause_count == 1) begin

mod_pixel_addr <= pixel_addr;

read_flash <= 0;

read_flash <= 1;

end if (flash_pause_count == 5) begin

pixel_p1 <= save_data;

mod_pixel_addr <= (pixel_addr+1'b1);

read_flash <= 0;

read_flash <= 1;

end if (flash_pause_count == 10) begin

pixel_p2 <= save_data;

mod_pixel_addr <= (pixel_addr+2'b10);

read_flash <= 0;

read_flash <= 1;

end if (flash_pause_count == 15) begin

pixel_p3 <= save_data;

flash_pause_done <= 1;

read_flash <= 0;

end

end else begin

flash_pause_count <= 0;

end

flash_pause_done <= 0;

end

I get a latch warning here... and...

Error (10200): Verilog HDL Conditional Statement error at RealTime2.v(264): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct

always @(posedge read_flash or posedge f_done) begin

//trigger read

if (read_flash == 1) begin

data_addr <= mod_pixel_addr;

f_read <= 1;

end else begin

f_read <= 0;

end

end

--- Quote Start ---

So I built this... but....

always @(posedge read_flash_pixel or posedge flash_pause_done) begin

if (read_flash_pixel) begin

flash_pause <= 1;

end else begin

flash_pause <= 0;

end

end

always @(posedge CLOCK_50) begin

if(flash_pause == 1) begin

flash_pause_count <= flash_pause_count+1;

if (flash_pause_count == 1) begin

mod_pixel_addr <= pixel_addr;

read_flash <= 0;

read_flash <= 1;

end if (flash_pause_count == 5) begin

pixel_p1 <= save_data;

mod_pixel_addr <= (pixel_addr+1'b1);

read_flash <= 0;

read_flash <= 1;

end if (flash_pause_count == 10) begin

pixel_p2 <= save_data;

mod_pixel_addr <= (pixel_addr+2'b10);

read_flash <= 0;

read_flash <= 1;

end if (flash_pause_count == 15) begin

pixel_p3 <= save_data;

flash_pause_done <= 1;

read_flash <= 0;

end

end else begin

flash_pause_count <= 0;

end

flash_pause_done <= 0;

end

I get a latch warning here... and...

Error (10200): Verilog HDL Conditional Statement error at RealTime2.v(264): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct

always @(posedge read_flash or posedge f_done) begin

//trigger read

if (read_flash == 1) begin

data_addr <= mod_pixel_addr;

f_read <= 1;

end else begin

f_read <= 0;

end

end

--- Quote End ---

Hi,

you have to define what should happend to "data_adder" in the else branch.

Kind regards

GPL

I'm not a Verilog expert, but I think your problem is with this line:

always @(posedge read_flash_pixel or posedge flash_pause_done)

First of all you have two clocks driving the same process, and this is not a good coding practice.

Then, one of the clocks (read_flash_pixel) is also used in the conditional inside the process: the error message seems to refer to this.

I'd use the always @(posedge CLOCK_50) for this process, too.

Every clock cycle you can store read_flash_pixel and flash_pause_done levels and in the next one you test the edge condition.

--- Quote Start ---

I'm not a Verilog expert, but I think your problem is with this line:

always @(posedge read_flash_pixel or posedge flash_pause_done)

First of all you have two clocks driving the same process, and this is not a good coding practice. Then, one of the clocks (read_flash_pixel) is also used in the conditional inside the process: the error message seems to refer to this.

--- Quote End ---

To clarify this point. It's legal Verilog syntax, not involving two clocks. But I guess, it's not what the original poster wanted, he may have misunderstood this common Verilog construct himself.

read_flash_pixel is not a clock, if it's used together with if (read_flash == 1), it's an asynchronous input. The respective VHDL code is

process(read_flash_pixel , posedge f_done);
begin
if read_flash_pixel = '1' then
--
elsif rising_edge(posedge f_done) then
--
end if;
end process;

I think, it's useful to know the basic constructs of a "foreign" language, otherwise you can't read the code.