Verilog delays~?

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I'm not a Verilog expert, but I think your problem is with this line:

always @(posedge read_flash_pixel or posedge flash_pause_done)

First of all you have two clocks driving the same process, and this is not a good coding practice. Then, one of the clocks (read_flash_pixel) is also used in the conditional inside the process: the error message seems to refer to this.

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To clarify this point. It's legal Verilog syntax, not involving two clocks. But I guess, it's not what the original poster wanted, he may have misunderstood this common Verilog construct himself.

read_flash_pixel is not a clock, if it's used together with if (read_flash == 1), it's an asynchronous input. The respective VHDL code is

process(read_flash_pixel , posedge f_done);
begin
if read_flash_pixel = '1' then
--
elsif rising_edge(posedge f_done) then
--
end if;
end process;

I think, it's useful to know the basic constructs of a "foreign" language, otherwise you can't read the code.