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Altera_Forum's avatar
Altera_Forum
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15 years ago

Verilog delays~?

Hello, I'm writing a verilog prog on my DE1 to read off the flash memory... but I cannot figure out how I can wait until the read completes before continuing in my program. I set f_read = 1 o...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Cool! I ended up using the negedge CLOCK_50 so it gets done before the next clock cycle on the next step of the setup :-) that seems to work nicely :D