Verilog delays~?

I'm not a Verilog expert, but I think your problem is with this line:

always @(posedge read_flash_pixel or posedge flash_pause_done)

First of all you have two clocks driving the same process, and this is not a good coding practice.

Then, one of the clocks (read_flash_pixel) is also used in the conditional inside the process: the error message seems to refer to this.

I'd use the always @(posedge CLOCK_50) for this process, too.

Every clock cycle you can store read_flash_pixel and flash_pause_done levels and in the next one you test the edge condition.