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Altera_Forum's avatar
Altera_Forum
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15 years ago

Verilog delays~?

Hello, I'm writing a verilog prog on my DE1 to read off the flash memory... but I cannot figure out how I can wait until the read completes before continuing in my program. I set f_read = 1 o...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I'm not a Verilog expert, but I think your problem is with this line: 

always @(posedge read_flash_pixel or posedge flash_pause_done)

First of all you have two clocks driving the same process, and this is not a good coding practice.

Then, one of the clocks (read_flash_pixel) is also used in the conditional inside the process: the error message seems to refer to this.

I'd use the always @(posedge CLOCK_50) for this process, too.

Every clock cycle you can store read_flash_pixel and flash_pause_done levels and in the next one you test the edge condition.