--- Quote Start ---
So I built this... but....
always @(posedge read_flash_pixel or posedge flash_pause_done) begin
if (read_flash_pixel) begin
flash_pause <= 1;
end else begin
flash_pause <= 0;
end
end
always @(posedge CLOCK_50) begin
if(flash_pause == 1) begin
flash_pause_count <= flash_pause_count+1;
if (flash_pause_count == 1) begin
mod_pixel_addr <= pixel_addr;
read_flash <= 0;
read_flash <= 1;
end if (flash_pause_count == 5) begin
pixel_p1 <= save_data;
mod_pixel_addr <= (pixel_addr+1'b1);
read_flash <= 0;
read_flash <= 1;
end if (flash_pause_count == 10) begin
pixel_p2 <= save_data;
mod_pixel_addr <= (pixel_addr+2'b10);
read_flash <= 0;
read_flash <= 1;
end if (flash_pause_count == 15) begin
pixel_p3 <= save_data;
flash_pause_done <= 1;
read_flash <= 0;
end
end else begin
flash_pause_count <= 0;
end
flash_pause_done <= 0;
end
I get a latch warning here... and...
Error (10200): Verilog HDL Conditional Statement error at RealTime2.v(264): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct
always @(posedge read_flash or posedge f_done) begin
//trigger read
if (read_flash == 1) begin
data_addr <= mod_pixel_addr;
f_read <= 1;
end else begin
f_read <= 0;
end
end
--- Quote End ---
Hi,
you have to define what should happend to "data_adder" in the else branch.
Kind regards
GPL
Honored Contributor
