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M3511's avatar
M3511
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4 years ago
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Using 644.53125 MHz clock on Stratix V Dev Board

Hi,

I need to use the 644.53125 MHz clock on the Stratix V development board. Do I just need to connect to pins AB34/AB35? Or do I also need to set it to that particular frequency? Not completely clear on whether the U46 programmable LVDS quad-clock will already have 644.53125MHz on the pins when first powered up.

Thank you

  • AR_A_Intel's avatar
    AR_A_Intel
    4 years ago

    Hi

    Thanks for update. Based on my understanding, dev kit board already pre-programed with certain default clock frequency value. The default clock frequency value can be checked via either user guide doc or from schematic. U46 CLK1 output 644.5313MHz by default this mean clock generator chip (for example U46) will generate clk1 output = 644.5313MHz directly. No need to set anything.


8 Replies

  • AR_A_Intel's avatar
    AR_A_Intel
    Icon for Super Contributor rankSuper Contributor
    4 years ago

    Hi

    Thanks for update. Based on my understanding, dev kit board already pre-programed with certain default clock frequency value. The default clock frequency value can be checked via either user guide doc or from schematic. U46 CLK1 output 644.5313MHz by default this mean clock generator chip (for example U46) will generate clk1 output = 644.5313MHz directly. No need to set anything.


    • M3511's avatar
      M3511
      Icon for New Contributor rankNew Contributor
      4 years ago

      Thank you. I believe you are right.

      Also, does it matter whether the QSFP breakout cable is active optical or passive copper?

  • M3511's avatar
    M3511
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    4 years ago

    Also, does the QSFP breakout cable need to be active optical instead of passive copper?

  • M3511's avatar
    M3511
    Icon for New Contributor rankNew Contributor
    4 years ago

    Does it matter whether the QSFP breakout cable is active optical or passive copper?

  • AR_A_Intel's avatar
    AR_A_Intel
    Icon for Super Contributor rankSuper Contributor
    4 years ago

    Hi

    Based on m understanding, it shouldn’t matter and it depends on whether you using it with Intel FPGA IP or your own IP.

    If you are using Intel FPGA IP then you could check the IP user guide doc for further clarification.


  • AR_A_Intel's avatar
    AR_A_Intel
    Icon for Super Contributor rankSuper Contributor
    4 years ago

    Thanks for your update. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you