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Altera_Forum's avatar
Altera_Forum
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16 years ago

Trouble loading User design to FPGA

Hi,

preface: I currently have a design that runs great on a NiosII CycloneII Dev Board. I am trying to port my design over to the NiosII StratixII Dev Board, but was running into problems (those problems are probably for a different thread). I decided that I should first try to program a simple design to the StratixII Dev Board, just to build up my confidence of the Board.

problem: Every time I try to program my design to the FPGA on the NiosII StratixII Dev Board, it programs the device "successfully" but then loads the factory default design.

question: What am I doing wrong? My design has one top level block that takes in Clock (on pin B13) and Reset (on pin C5) and outputs a counter value on the Proto1 pins.

Please help!!!

Thanks,

-Ben

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    What are you using to program the part? Are you programming the FPGA directly or a flash?

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I am trying to program the FPGA directly through the JTAG port. The FPGA is "successfully" programmed and then it runs for about half a second and then the board stops and programs itself with the factory configuration.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Yes, I am using J24 as the JTAG header.

    Do you think it is something with my clock or reset pin?

    I will try to program the same design onto the old CycloneII Dev Board that I use, just to make sure my simple code works.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I know that dev. board has a MAX device that loads the configuration from flash. Is that defeating your load? Maybe it triggers off of the JTAG signals. Seems unlikely but you never know.

    The Quartus project must be setup properly since it thinks it programs successfully.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    I looked at the link that stefan__ posted with a possible solution to this problem. His suggested solution was to make this change:

    --- Quote Start ---

    quartus menu assignments > device > device and pin options... > unused pins > Reserve all unused pins: As input tri-stated

    --- Quote End ---

    as opposed to leaving the pins as output driving ground. I made this change, but the configuration problem still remained.

    My solution was to program my FPGA configuration into the Factory Configuration space of the Flash (offset 0x00C00000) instead of the User Application Space (offset 0x00000000). This way when the Flash Programming fails to load the User Design from the User Application Space and it defaults to loading the Factory Configuration, it loads the User Application ;)