Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Trouble loading User design to FPGA

Hi, preface: I currently have a design that runs great on a NiosII CycloneII Dev Board. I am trying to port my design over to the NiosII StratixII Dev Board, but was running into problems (th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I looked at the link that stefan__ posted with a possible solution to this problem. His suggested solution was to make this change:

--- Quote Start ---

quartus menu assignments > device > device and pin options... > unused pins > Reserve all unused pins: As input tri-stated

--- Quote End ---

as opposed to leaving the pins as output driving ground. I made this change, but the configuration problem still remained.

My solution was to program my FPGA configuration into the Factory Configuration space of the Flash (offset 0x00C00000) instead of the User Application Space (offset 0x00000000). This way when the Flash Programming fails to load the User Design from the User Application Space and it defaults to loading the Factory Configuration, it loads the User Application ;)