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Altera_Forum
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16 years ago

Trouble loading User design to FPGA

Hi, preface: I currently have a design that runs great on a NiosII CycloneII Dev Board. I am trying to port my design over to the NiosII StratixII Dev Board, but was running into problems (th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Yes, I am using J24 as the JTAG header.

Do you think it is something with my clock or reset pin?

I will try to program the same design onto the old CycloneII Dev Board that I use, just to make sure my simple code works.